1. Field of the Invention
The present invention generally relates to a system and method for testing the reliability of integrated circuit structures and more particularly to an improved wafer-level dielectric reliability test system and method utilizing the contactless detection of optical signal (photon emission) instead of conventional electrical signals such as voltage, current, and resistance to determine time dependent device failure for large-scale reliability evaluations. The invention isolates defective devices through the use of fuses with a specific test structure design allowing the remaining devices to be continuously emission tested.
2. Description of the Related Art
Reliability evaluation processes such as time-dependent dielectric breakdown stress testing are required for semiconductor manufacturing processes. The purpose of this testing is to ensure qualified technology and to prevent defective and less reliable chips from reaching the user. Current processes heavily utilize constant voltage or current stress testing to evaluate the reliability of the oxide. For the wafer-level stress testing approach, a probe test apparatus is used. In such testing, the probes are brought into physical contact with the electrical pads of one chip of a large number of semiconductor chips on the semiconductor wafer. A constant voltage or a constant current is then applied to one chip at a time by using the probe test apparatus. An output electrical signal (current for constant voltage stress testing or voltage for constant current stress testing) from the stressed chip is monitored by an electric meter thereby testing the wear-out and breakdown characteristics of each semiconductor chip in series. A sudden current increase during the constant voltage stress or a sudden voltage drop during the constant current stress is defined as breakdown of the device.
With continuously aggressive shrinking in very large scale integration (VLSI), dielectric breakdown is considered a major reliability issue for ultra thin gate oxides and storage node dielectrics. An accurate lifetime projection is of great importance to the evaluation of advanced metal oxide semiconductor field, effect transistor (MOSFET) technologies. With the aggressive decreasing of the device dielectric thickness, high leakage current at the stress level, due to direct tunneling, and soft breakdown during the stress impose great challenges for the traditional dielectric time-to-breakdown reliability stress. They introduce more uncertainties and limitations for failure time detection during electrical stress testing. On the other hand, generally, statistically independent sample sizes directly affect the accuracy of oxide stress results. The probability of determining the correct distribution parameters of the population increases with sample size, and a large sample size tightens the confidence bounds. Unfortunately, large-scale oxide reliability evaluations require a large pool of stress equipment and tremendous amount of stress time. The current oxide time-to-breakdown measurements are tedious, costly, and time-consuming.
Using electrical signals such as current and voltage as breakdown detection becomes more difficult as device dielectric thickness is aggressively reduced. Ultra-high leakage current due to direct tunneling in thin dielectric film greatly decreases the breakdown signal to base current ratio. The sudden increase of a stress current signal is much less significant when compared with the base stress current for thin dielectric films and, therefore, is very hard to accurately detect. The use of a small area test device instead of a large area test device is required to overcome the detection resolution problem, as leakage current is proportional to the device area. However, a small test area could greatly reduce the probability of catching the extrinsic defects and it also could limit the size range of area scaling.
With decreasing dielectric thicknesses, dielectric soft breakdown commonly occurs before hard breakdown. The breakdown current after soft breakdown is orders of magnitude smaller than that after hard breakdown and usually induces only a stress current oscillation instead of sharp increase. Thus, soft breakdown of thin dielectric films further aggravates detection problems associated with high stress currents. Furthermore, the oscillation of current during stress testing could be induced by other non-catastrophic events instead of soft and hard breakdown for ultra-thin dielectric films, which raises another great uncertainty for the failure time detection for such films. Therefore, using conventional dielectric time-to-failure reliability stress methodology is of great concern.
For wafer-level stress testing, in order to test all the chips on the wafer, a wafer chuck on which the semiconductor wafer is held is moved vertically up and down and stepped by a distance corresponding to one chip every time after a test on a chip is completed. A disadvantage of wafer-level stress testing is the fact that only one chip is stressed at a time. Therefore, the measurements are time-consuming and the sample sizes are forced to be limited in order to finish the whole stress test within a reasonable time frame. Although module level electrical stress methods could be utilized to procure a large sample size requirement, the cost to build this kind of system with a large quantity of power sources and sophisticated test software is high. Cutting a semiconductor wafer into chips and packaging them increases the cost and time which is also a concern. Furthermore, the reliability of this kind of complex system with multiple power sources is questionable. Thus, while electrical module level stress testing could provide massive parallel stress, the cost (power sources, hardware design, software, maintenance, etc.) of test equipment and module build is also very high. In addition, module level stress testing is not practical lines for process monitoring, controlling, and device screening. Physical defect location, device level process uniformity, and the physical nature of the failure from damaged devices also cannot be determined using such conventional electrical methods.
In order to solve the disadvantages and drawbacks of conventional dielectric reliability tests, there is a need for a new system and methodology that stresses a large number of devices, yet is accurate, simple, reliable, economical, and provides more related information such as physical breakdown locations, signatures of different failures, and device level process uniformity.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional time-dependent dielectric breakdown (TDDB) reliability stress method and hardware systems, the present invention has been devised, and it is an object of the present invention to provide a method and apparatus for better determining dielectric breakdown in a semiconductor device. Instead of monitoring electrical signal change as failure or breakdown detection, the present invention uses an optical signal detection source. The present invention results in a more effective, more precise, faster, and much simpler evaluation method for oxide wear-out and reliability studies.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a method which tests devices on a wafer. The invention first applies an electrical bias by bringing a testing probe into contact with an outer connecting terminal of all the devices under test on the wafer in parallel. After a long period of degradation, the dielectric eventually undergoes a catastrophic condition to form a conductive filament in the dielectric due to large current flow, which results in a burst of light emission that can easily be detected, recorded, and mapped by photo emission microscopy (e.g. see, U.S. Pat. No. 6,184,046, U.S. Pat. No. 5,981,967, U.S. Pat. No. 4,845,425, JAP PAT. 10223707 incorporated herein by reference). The invention therefore monitors optical signals (emitted light) directly from a breakdown spot within a device, instead of measuring indirect electrical signals, such as voltage or current from the whole device. One optical photon sensor or an integrated photon sensor array is designed to detect light emission from many devices across the wafer simultaneously, in contrast to the conventional electrical method that uses one electrical meter per device or that requires an extra scanner for such parallel stress testing. The time of emitted light change indicates the time of oxide breakdown, and the location of emitted light from the failure device indicates the location of the breakdown. The system records time-based optical signals of the emitted light for all the devices across the wafer.
The invention which uses optical signals instead of electrical signals to detect dielectric time-dependent failure during TDDB reliability stress testing and can be directly incorporated into conventional wafer-level TDDB tests to improve the accuracy of thin dielectric breakdown detection during the stress testing. With the inventive test design in conjunction with the optical signal detection system, the invention further enhances the efficieny of TDDB reliability testing by stressing a large number of devices in parallel on the wafer-level with very limited hardware. During the stress testing, the invention terminates connections between the electrical bias and the failing devices. The invention then continues the monitoring and continues terminating failing devices during the duration of the testing. Time-based images are available in real time during the testing. The invention maps device defects across the wafer on a time-line basis. The invention connects the devices in parallel on the wafer. The terminating process opens fuses to electrically isolate the failed devices from the rest of the devices under test.
The invention also includes a system that tests devices on a wafer. The system has a power source unit that applies one or more electrical biases to all the devices under test using the specific designed test site, and a specialized photon sensor, or photon sensor array, that detects optical signals from many devices under the test across the wafer. The system has an image processor that converts the emitted light into emitted light signals, and a digital recording system that provides time resolution of light intensity change during the stress. A selectable lens optic system is coupled to an image intensifier, which is in turn connected to a spectrum analyzer to determine the wavelength dependent photon intensity. The emitted light signals indicate the times and locations of the failure formation within the devices. The spectral response of the detected light indicates the nature of the failures. The system also has a controller that terminates connections between the electrical bias and the defective devices.
With the real-time image recording, the time of oxide breakdown, the location of breakdown, the change of the light emission intensity during the stress, and the spectral response of the emitted light from breakdown spots provide extensive information regarding oxide wear-out and breakdown physics. With a minimum voltage source (one for regular constant voltage stress) or current source (one for regular constant current stress) and set up (multiple power sources could also be applied to more complex products) which is simple and reliable with very limited hardware, massively parallel stress testing for oxide breakdown can be easily achieved.